1. Technical Field
The present invention relates to field effect transistors (FETs), and more specifically, to planar dual-gate FETs (i.e., planar FETs that have main gates and back gates).
2. Related Art
The switching speed of a typical planar dual-gate FET depends on, among other things, the capacitances between the S/D regions and the back gate region of the typical planar dual-gate FET. The higher such capacitances, the longer it takes for switching (because it takes time for charging and discharging the capacitors), which is undesirable.
Therefore, there is a need for a planar dual-gate FET (and a method for fabricating the same) in which capacitances between the S/D regions and the back gate region are relatively lower than that of the prior art.